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NCP1500
Over Voltage Protection
NCP1500 has an overvoltage protection circuit that
protects the output during the PWM mode. Normally, in
PWM mode, the output switch will conduct at the onset of
every synchronization pulse. The minimum output duty
cycle is 3%. The output voltage will rise at minimum duty
cycle and a light load or no load condition is present at the
output. If the output rises more than 5% of the programmed
Note: PP ? Patent Pending
voltage, an overvoltage comparator will trip. This signal will
reset the PWM latch and hold it in a reset condition until the
output voltage decays below its threshold. The output will
then be allowed to switch at the next synchronization pulse.
This type of operation is usually referred to as PFM or skip
mode operation.
The following figure is a simulation of the regulator
during this condition:
3.6040
3.6000
3.5960
250.0 m
124.5 m
? 1.000 m
20 m
10 m
0.0
? 10 m
150 m
25.0 m
? 100 m
4.00
1.75
? 500 m
1.05150
1.05080
1.05010
4.0
2.0
V IN
Main FET Current
Inductor Current (F sync = 300 kHz)
Diode Current
V LX
V O (Set to 1 V)
Gate Voltage for Switching FET
0.0
175.00000
181.33333
187.66667
194.00000
200.33333
206.66667
213.00000
TIME ( m )
Figure 6. Waveforms of PFM Mode Operation During Over Voltage
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